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True Bipolar Input, Dual 1 s, 12-/14-Bit, 2-Channel SAR ADCs AD7366/AD7367
FEATURES
Dual 12-bit/14-bit, 2-channel ADC True bipolar analog inputs Programmable input ranges: 10 V, 5 V, 0 V to 10 V 12 V with 3 V external reference Throughput rate: 1 MSPS Simultaneous conversion with read in less than 1s High analog input impedance Low current consumption: 8.3 mA typical in normal mode 320nA typical in shutdown mode AD7366 72 dB SNR at 50 kHz input frequency 12-bit no missing codes AD7367 76 dB SNR at 50 kHz input frequency 14-bit no missing codes Accurate on-chip reference: 2.5 V 0.2% -40C to +85C operation High speed serial interface SPI-/QSPITM-/MICROWIRETM-/DSP-compatible iCMOS(R) process technology Available in a 24-lead TSSOP
FUNCTIONAL BLOCK DIAGRAM
VDD DCAP A AVCC DVCC
REF
BUF
AD7366/AD7367
VA1 MUX VA2 T/H 12-/14-BIT SUCCESSIVE APPROXIMATION ADC OUTPUT DRIVERS DOUTA
SCLK CNVST CONTROL LOGIC CS BUSY ADDR RANGE0 RANGE1 REFSEL VDRIVE
VB1
MUX
T/H
12-/14-BIT SUCCESSIVE APPROXIMATION ADC
OUTPUT DRIVERS
DOUTB
VB2
BUF
06703-001
AGND AGND
VSS
DCAP B
DGND
Figure 1.
GENERAL DESCRIPTION
The AD7366/AD7367 1 are dual, 12/14-bit, high speed, low power, successive approximation analog-to-digital converters (ADCs) that feature throughput rates up to 1 MSPS. The device contains two ADCs, each preceded by a 2-channel multiplexer, and a low noise, wide bandwidth track-and-hold amplifier. The AD7366/AD7367 are fabricated on the Analog Devices, Inc. industrial CMOS process (iCMOS(R) 2 ), which is a technology platform combining the advantages of low and high voltage CMOS. The process allows the AD7366/AD7367 to accept high voltage bipolar signals in addition to reducing power consumption and package size. The AD7366/AD7367 can accept true bipolar analog input signals in the 10 V range, 5 V range, and 0 V to 10 V range. The AD7366/AD7367 have an on-chip 2.5 V reference that can be disabled to allow the use of an external reference. If a 3 V reference is applied to the DCAPA and DCAPB pins, the AD7366/AD7367 can accept a true bipolar 12 V analog input. Minimum 12 V VDD and VSS supplies are required for the 12 V input range.
PRODUCT HIGHLIGHTS
1. The AD7366/AD7367 can accept true bipolar analog input signals, as well as 10 V, 5 V, 12 V (with external reference), and 0 V to +10 V unipolar signals. Two complete ADC functions allow simultaneous sampling and conversion of two channels. 1 MSPS serial interface; SPI-/QSPI-/DSP-/MICROWIREcompatible interface.
Throughput Rate 1 MSPS 500 kSPS 1 MSPS 500 kSPS Number of Channels Dual, 2-channel Dual, 2-channel Dual, 2-channel Dual, 2-channel
2. 3.
Table 1. Related Products
Device AD7366 AD7366-5 AD7367 AD7367-5
1 2
Resolution 12-Bit 12-Bit 14-Bit 14-Bit
Protected by U.S. Patent No. 6,731,232. iCMOS Process Technology. For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
AD7366/AD7367 TABLE OF CONTENTS
Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 16 Circuit Information.................................................................... 16 Converter Operation.................................................................. 16 Analog Inputs.............................................................................. 16 Transfer Function ....................................................................... 17 Typical Connection Diagram ................................................... 18 Driver Amplifier Choice ........................................................... 19 Reference ..................................................................................... 19 Modes of Operation ....................................................................... 20 Normal Mode.............................................................................. 20 Shutdown Mode ......................................................................... 21 Power-Up Times......................................................................... 21 Serial Interface ................................................................................ 22 Microprocessor Interfacing........................................................... 24 AD7366/AD7367 to ADSP-218x.............................................. 24 AD7366/AD7367 to ADSP-BF53x........................................... 24 AD7366/AD7367 to TMS320VC5506..................................... 25 AD7366/AD7367 to DSP563xx................................................ 25 Application Hints ........................................................................... 27 Layout and Grounding .............................................................. 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28
REVISION HISTORY
5/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7366/AD7367 SPECIFICATIONS
TA = -40C to +85C, AVCC = DVCC = 4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = -16.5 V to -11.5 V, VDRIVE = 2.7 V to 5.25 V, fSAMPLE = 1.12 MSPS, fSCLK = 48 MHz, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. Table 2. AD7366
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 1 Signal-to-Noise + Distortion Ratio (SINAD)1 Total Harmonic Distortion (THD)1 Spurious-Free Dynamic Range (SFDR)1 Intermodulation Distortion (IMD)1 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation1 SAMPLE AND HOLD Aperture Delay 2 Aperture Jitter2 Aperture Delay Matching2 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity (INL)1 Differential Nonlinearity (DNL)1 Positive Full-Scale Error1 Positive Full-Scale Error Match1 Zero Code Error1 Zero Code Error Match1 Negative Full-Scale Error1 Negative Full-Scale Error Match1 ANALOG INPUT Input Voltage Ranges (Programmed via RANGE Pins) DC Leakage Current Input Capacitance Input Impedance 0.01 9 13 260 2.5 125 1.2 Min 70 70 Typ 72 71 -85 -87 -88 -88 -90 10 40 100 35 8 12 0.5 0.25 1 1 1.5 0.1 0.5 1 1.5 0.1 1 1 1.5 0.1 1 0.5 7 6 Max Unit dB dB dB dB fa = 49 kHz, fb = 51 kHz dB dB dB ns ps ps MHz MHz Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB V V V A pF pF k M k M Test Conditions/Comments fIN = 50 kHz sine wave
-78 -78
@ 3 dB, 10 V range @ 0.1 dB, 10 V range
3 6
7 6
Guaranteed no missed codes to 12 bits 5 V and 10 V analog input range 0 V to 10 V analog input range Matching from ADC A to ADC B Channel to channel matching for ADC A and ADC B 5 V and 10 V analog input range 0 V to 10 V analog input range Matching from ADC A to ADC B Channel-to-channel matching for ADC A and ADC B 5 V and 10 V analog input range 0 V to 10 V analog input range Matching from ADC A to ADC B Channel-to-channel matching for ADC A and ADC B
10 5 0 to 10 1
When in track, 10 V range When in track, 5 V or 0 V to 10 V range For 10 V @1 MSPS For 10 V @100 kSPS For 5 V/ 0 V to 10 V @1 MSPS For 5 V/ 0 V to 10 V @100 kSPS
Rev. 0 | Page 3 of 28
AD7366/AD7367
Parameter REFERENCE INPUT/OUTPUT Reference Output Voltage3 Long-Term Stability Output Voltage Hysteresis1 Reference Input Voltage Range DC Leakage Current Input Capacitance DCAPA, DCAPB Output Impedance Reference Temperature Coefficient VREF Noise LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance2 CONVERSION RATE Conversion Time Track/Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VCC VDD VSS VDRIVE Normal Mode (Static) IDD ISS ICC Normal Mode (Operational) IDD ISS ICC Shutdown Mode IDD ISS ICC Power Dissipation Normal Mode (Operational) Min 2.495 Typ 2.5 150 50 0.01 25 17 7 6 20 0.7 x VDRIVE 0.01 6 VDRIVE - 0.2 0.01 8 0.4 1 +0.8 1 Max 2.505 Unit V ppm ppm V A pF pF ppm/C V rms V V A pF V V A pF ns ns MSPS MSPS V V V V A A mA mA mA mA A A A mW mW mW W VDD = +16.5 V VSS = -16.5 V VCC = 5.5 V fS = 1.12 MSPS VDD = +16.5 V VSS = -16.5 V VCC = 5.25 V, internal reference enabled VDD = +16.5 V VSS = -16.5 V VCC = 5.25 V VDD = +16.5 V, VSS = -16.5 V, VCC = 5.25 V, fS = 1.12 MSPS 10 V input range, fS = 1.12 MSPS, 5 V and 0 V to 10 V input range, fS = 1.12 MSPS VDD = +16.5 V, VSS = -16.5 V, VCC = 5.25 V Test Conditions/Comments 0.2% max @ 25C For 1000 hours
2.5
3.0 1
External reference applied to Pin DCAPA/Pin DCAPB 5 V and 10 V analog input range 0 V to 10 V analog input range
25
Bandwidth = 3 kHz
VIN = 0 V or VDRIVE
610 140 1.12 1 4.75 +11.5 -16.5 2.7 370 40 1.5 1.8 1.5 5 0.01 0.01 0.3 5.25 +16.5 -11.5 5.25 550 60 1.8 2.0 1.6 5.6 1 1 2 88.8 50 70 1.9
Full-scale step input For 4.75 V VDRIVE 5.25 V, fSCLK = 48 MHz For 2.7 V VDRIVE < 4.75 V, fSCLK = 35 MHz Digital Inputs = 0 V or VDRIVE See Table 7 See Table 7 See Table 7
Shutdown Mode
1 2
43.5
See the Terminology section. Sample tested during initial release to ensure compliance. 3 Refers to Pin DCAPA or Pin DCAPB specified for 25oC.
Rev. 0 | Page 4 of 28
AD7366/AD7367
TA = -40C to +85C, AVCC = DVCC = 4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = -16.5 V to -11.5 V, VDRIVE = 2.7 V to 5.25 V, fSAMPLE = 1 MSPS, fSCLK = 48 MHz, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. Table 3. AD7367
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 1 Signal-to-Noise + Distortion Ratio (SINAD)1 Total Harmonic Distortion (THD)1 Spurious-Free Dynamic Range (SFDR)1 Intermodulation Distortion (IMD)1 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation1 SAMPLE AND HOLD Aperture Delay 2 Aperture Jitter2 Aperture Delay Matching2 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity (INL)1 Differential Nonlinearity (DNL)1 Positive Full-Scale Error1 Positive Full-Scale Error Match1 Min 74 73 Typ 76 75 -84 -87 -91 -89 -90 10 40 100 35 8 14 2 0.5 4 5 3 0.2 1 5 3 0.2 4 5 3 0.2 3.5 0.90 20 20 Max Unit dB dB dB dB fa = 49 kHz, fb = 51 kHz dB dB dB ns ps ps MHz MHz Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB Test Conditions/Comments fIN = 50 kHz sine wave
-78 -79
@ 3 dB, 10 V range @ 0.1 dB, 10 V range
Zero Code Error1 Zero Code Error Match1
10 20
Negative Full-Scale Error1 Negative Full-Scale Error Match1
20 20
Guaranteed no missed codes to 14 bits 5 V and 10 V analog input range 0 V to 10 V analog input range Matching from ADC A to ADC B Channel to channel matching for ADC A and ADC B 5 V and 10 V analog input range 0 V to 10 V analog input range Matching from ADC A to ADC B Channel to channel matching for ADC A and ADC B 5 V and 10 V analog input range 0 V to 10 V analog input range Matching from ADC A to ADC B Channel-to-channel matching for ADC A and ADC B
ANALOG INPUT Input Voltage Ranges (Programmed via RANGE Pins) DC Leakage Current Input Capacitance Input Impedance 0.01 9 13 260 2.5 125 1.2
10 5 0 to 10 1
V V V A pF pF k M k M
See Table 7 When in track, 10 V range When in track, 5 V or 0 V to 10 V range For 10 V @ 1 MSPS For 10 V @ 100 kSPS For 5 V/0 V to 10 V @ 1 MSPS For 5 V/0 V to 10 V @ 100 kSPS
Rev. 0 | Page 5 of 28
AD7366/AD7367
Parameter REFERENCE INPUT/OUTPUT Reference Output Voltage3 Long-Term Stability Output Voltage Hysteresis1 Reference Input Voltage Range DC Leakage Current Input Capacitance DCAPA, DCAPB Output Impedance Reference Temperature Coefficient VREF Noise LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance2 CONVERSION RATE Conversion Time Track/Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VCC VDD VSS VDRIVE Normal Mode (Static) IDD ISS ICC Normal Mode (Operational) IDD ISS ICC Shutdown Mode IDD ISS ICC Power Dissipation Normal Mode (Operational) Min 2.495 Typ 2.5 150 50 0.01 25 17 7 6 20 0.7 x VDRIVE 0.01 6 VDRIVE - 0.2 0.01 8 0.4 1 0.8 1 Max 2.505 Unit V ppm ppm V A pF pF ppm/C V rms V V A pF V V A pF ns ns MSPS kSPS V V V V A A mA mA mA mA A A A mW mW mW W Test Conditions/Comments 0.2% max @ 25C For 1000 hours
2.5
3.0 1
External reference applied to DCAPA/Pin DCAPB 5 V and 10 V analog input range 0 V to 10 V analog input range
25
Bandwidth = 3 kHz
VIN = 0 V or VDRIVE
680 140 1 900 4.75 +11.5 -16.5 2.7 370 40 1.5 1.8 1.5 5 0.01 0.01 0.3 80.7 50 70 1.9 5.25 +16.5 -11.5 5.25 550 60 1.8 2.0 1.6 5.6 1 1 2 88.8
Full-scale step input; For 4.75 V VDRIVE 5.25 V, fSCLK = 48 MHz For 2.7 V VDRIVE < 4.75 V, fSCLK = 35 MHz Digital Inputs = 0 V or VDRIVE See Table 7 See Table 7 See Table 7
VDD = +16.5 V VSS = -16.5 V VCC = 5.5 V fS = 1 MSPS VDD = +16.5 V VSS = -16.5 V VCC = 5.25 V, internal reference enabled VDD = +16.5 V VSS = -16.5 V VCC = 5.25 V VDD = +16.5 V, VSS = -16.5 V, VCC = 5.25 V 10 V input range, fS = 1 MSPS 5 V and 0 V to 10 V input range, fS = 1 MSPS VDD = +16.5 V, VSS = -16.5 V, VCC = 5.25 V
Shutdown Mode
1 2
43.5
See the Terminology section. Sample tested during initial release to ensure compliance. 3 Refers to Pin DCAPA or Pin DCAPB.
Rev. 0 | Page 6 of 28
AD7366/AD7367
TIMING SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = -16.5 V to -11.5 V, VDRIVE = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted. 1 Table 4.
Parameter tCONVERT Limit at TMIN, TMAX 2.7 V VDRIVE < 4.75 V 4.75 V VDRIVE 5.25 V Unit Test Conditions/Comments Conversion time, internal clock. CONVST falling edge to BUSY falling edge For the AD7367 For the AD7366 Frequency of serial read clock Minimum quiet time required between the end of serial read and the start of the next conversion Minimum CONVST low pulse CONVST falling edge to BUSY rising edge BUSY falling edge to MSB valid once CS is low for t4 prior to BUSY going low Delay from CS falling edge until Pin 1 (DOUTA) and Pin 23 (DOUTB) are three-state disabled Data access time after SCLK falling edge SCLK to data valid hold time SCLK low pulse width SCLK high pulse width CS rising edge to DOUTA, DOUTB, high impedance Power up time from shutdown mode; time required between CONVST rising edge and CONVST falling edge
fSCLK tQUIET t1 t2 t3 t4 t5 2 t6 t7 t8 t9 tPOWER-UP
1
680 610 10 35 30 10 40 0 10 20 7 0.3 x tSCLK 0.3 x tSCLK 10 70
680 610 10 48 30 10 40 0 10 14 7 0.3 x tSCLK 0.3 x tSCLK 10 70
ns max ns max kHz min MHz max ns min ns min ns min ns min ns max ns max ns min ns min ns min ns max s
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Terminology section and Figure 25. 2 The time required for the output to cross is 0.4 V or 2.4 V.
Rev. 0 | Page 7 of 28
AD7366/AD7367 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter VDD to AGND, DGND VSS to AGND, DGND VDRIVE to DGND VDD to AVCC AVCC to AGND, DGND DVCC to AVCC DVCC to DGND VDRIVE to AGND AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to GND DCAPB, DCAPB Input to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature TSSOP Package JA Thermal Impedance JC Thermal Impedance Pb-free Temperature, Soldering Reflow ESD
1
Rating -0.3 V to +16.5 V -16.5 V to +0.3 V -0.3 V to DVCC (VCC - 0.3 V) to +16.5 V -0.3 V to +7 V -0.3 V to +0.3 V -0.3 V to +7 V -0.3 V to DVCC -0.3 V to +0.3 V VSS - 0.3 V to VDD + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to A VCC + 0.3 V 10 mA -40C to +85C -65C to +150C 150C 128C/W 42C/W 260(+0)C 1.5 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Transient currents of up to 100 mA will not cause latch-up.
Rev. 0 | Page 8 of 28
AD7366/AD7367 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DOUTA VDRIVE DVCC RANGE1 RANGE0 ADDR AGND AVCC DCAP A
1 2 3 4 5 6 24 23 22
DGND DOUTB BUSY CNVST
SCLK TOP VIEW (Not to Scale) 19 CS 18 REFSEL 7
20 8 9 17 16 15 14 13
AD7366/ AD7367
21
AGND DCAP B VDD
06703-002
VSS 10 VA1 11 VA2 12
VB1 VB2
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1, 23 Mnemonic DOUTA, DOUTB Description Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input and 12 SCLK cycles are required to access the data from the AD7366 while 14 SCLK cycle are required for the AD7367. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366 and 14 bits for the AD7367 and is provided MSB first. If CS is held low for a further 12 SCLK cycles for the AD7366 or 14 SCLK cycles for the AD7367, on either DOUTA or DOUTB, the data from the other ADC follows on that DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one serial port. See the Serial Interface section for more information. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different to the voltage at AVCC and DVCC, but should never exceed either by more than 0.3 V. To achieve a throughput rate of 1.12 MSPS for the AD7366 or 1 MSPS for the AD7367, VDRIVE must be greater than or equal to 4.75 V. Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled to DGND. Place 10 F and 100 nF decoupling capacitors on the DVCC pin. Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog input channels. See the Analog Inputs section and Table 8 for details. Multiplexer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADCB. The logic state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion. Analog Ground. Ground reference point for all analog circuitry on the AD7366/AD7367. All analog input signals and any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and DVCC voltages should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled to AGND. Place 10 F and 100 nF decoupling capacitors on the AVCC pin. Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective ADC. For best performance, it is recommended to use a 680 nF decoupling capacitor on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally to the rest of a system. Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure of the AD7366/AD7367. The supply must be less than a maximum voltage of -11.5 V for all input ranges. See Table 7 for further details. Place 10 F and 100 nF decoupling capacitors on the VSS pin. Analog Inputs of ADC A. These are both single-ended analog inputs. The analog input range on these channels is determined by the RANGE0 and RANGE1 pins. Analog Inputs of ADC B. These are both single-ended analog inputs. The analog input range on these channels is determined by the RANGE0 and RANGE1 pins. Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure AD7366/AD7367. The supply must be greater than a minimum voltage of 11.5 V for all the analog input ranges. See Table 7 for further details. Place 10 F and 100 nF decoupling capacitors on the VDD pin.
Rev. 0 | Page 9 of 28
2
VDRIVE
3
DVCC
4, 5 6
RANGE1, RANGE0 ADDR
7, 17
AGND
8
AVCC
9, 16
DCAPA, DCAPB
10
VSS
11, 12 13, 14 15
VA1, VA2 VB2, VB1 VDD
AD7366/AD7367
Pin No. 18 Mnemonic REFSEL Description Internal/External Reference Selection, Logic Input. If this pin is tied to logic high, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to decoupling capacitors. If the REFSEL pin is tied to GND, an external reference can be supplied to the AD7366/ AD7367 through the DCAPA and/or DCAPB pins. Chip Select, Active Low Logic Input. This input frames the serial data transfer. When CS is logic low, the output bus is enabled and the conversion result is output on DOUTA and DOUTB. Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7366/AD7367. Conversion Start; Logic Input. This pin is edge triggered. On the falling edge of this input, the track/hold goes into hold mode and the conversion is initiated. If CNVST is low at the end of a conversion, the part goes into power-down mode. In this case, the rising edge of CNVST instructs the part to power up again. Busy Output. BUSY transitions high when a conversion is started and remains high until the conversion is complete. Digital Ground. This is the ground reference point for all digital circuitry on the AD7366/AD7367. The DGND pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
19 20 21
CS
SCLK CNVST
22 24
BUSY DGND
Rev. 0 | Page 10 of 28
AD7366/AD7367 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, unless otherwise noted.
1.0 0.8 0.6
DNL ERROR (LSB)
-76 0V TO 10V RANGE
0.4
THD (dB)
-78 10V RANGE 5V RANGE
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2000 4000 6000 8000 CODE AVCC = 5V, DVCC = 5V VDD = 15V, VSS = -15V VDRIVE = 3V fS = 1MSPS TA = 25C INTERNAL REFERENCE
06703-003
-80
-82 AVCC = 5V, DVCC = 5V VDD = 15V, VSS = -15V VDRIVE = 3V fS = 1MSPS INTERNAL REFERENCE 100 ANALOG INPUT FREQUENCY (kHz) 1000
06703-006 06703-008 06703-007
-84
10000 12000 14000 16000
-86 10
Figure 3. AD7367 Typical DNL
Figure 6. THD vs. Analog Input Frequency
2.0
-66
1.5 1.0
INL ERROR (LSB)
-71
AVCC = 5V, DVCC = 5V VDD = 15V, VSS = -15V VDRIVE = 3V fS = 1MSPS INTERNAL REFERENCE 5V RANGE
RIN = 2000
0.5
THD (dB)
RIN = 1300 -76 RIN = 3000 RIN = 5100 RIN = 470
0 -0.5 -1.0 -1.5 -2.0 AVCC = 5V, DVCC = 5V VDD = 15V, VSS = -15V VDRIVE = 3V fS = 1MSPS TA = 25C INTERNAL REFERENCE 0 2000 4000 6000 8000 CODE 10000 12000 14000 16000
06703-004
-81 RIN = 56 -86 10 RIN = 3900 100 ANALOG INPUT FREQUENCY (kHz) 1000 RIN = 240
Figure 4. AD7367 Typical INL
Figure 7. THD vs. Analog Input Frequency for Various Source Impedances
0 -20 -40 -60
SINAD (dB)
AVCC = 5V, DVCC = 5V VDD = 15V, VSS = -15V VDRIVE = 3V fS = 1MSPS, fIN = 50kHz INTERNAL REFERENCE SNR = 76dB, SINAD = 73dB
77
75
10V RANGE
(dB)
73
0V TO 10V RANGE
-80 -100 -120
71 AVCC = 5V, DVCC = 5V VDD = 15V, VSS = -15V VDRIVE = 3V fS = 1MSPS INTERNAL REFERENCE 100 ANALOG INPUT FREQUENCY (kHz)
69
-140 -160
67 10
5V RANGE 1000
0
5000
10000 15000 20000 25000 30000 35000 40000 45000 50000
FREQUENCY (kHz)
Figure 5. AD7367 FFT
06703-005
Figure 8. SINAD vs. Analog Input Frequency
Rev. 0 | Page 11 of 28
AD7366/AD7367
-70
-70 VCC, ADC A -80 100mV p-p SINE WAVE ON AVCC NO DECOUPLING CAPACITOR VDD = 15V, VSS = -15V VCC, ADC B VDRIVE = 3V fS = 1MSPS VDD, ADC B -100 VDD, ADC A -110 VSS, ADC A
06703-011
06703-012
CHANNEL-TO-CHANNEL ISOLATION (dB)
-75 -80 -85 -90 -95 -100 -105 -110 5V RANGE 0V TO 10V RANGE
PSRR (dB)
-90
10V RANGE AVCC = 5V, DVCC = 5V VDD = 15V, VSS = -15V VDRIVE = 3V fS = 1MSPS INTERNAL REFERENCE
06703-009
VSS, ADC B
0
100
200
300
400
500
600
-120
0
200
400
600
800
1000
1200
FREQUENCY OF INPUT NOISE (kHz)
SUPPLY RIPPLE FREQUENCY (kHz)
Figure 9. Channel-to-Channel Isolation
Figure 11. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
110000 100000 90000 80000 70000 60000 50000 40000 30000 20000 10000 8191 8192 8193
31 CODES
106091 CODES
80
344 CODES
60
ANALOG INPUT CURRENT (A)
AVCC = 5V, DVCC = 5V VDD = 15V, VSS = -15V VDRIVE = 3V fS = 1MSPS INTERNAL REFERENCE
VIN = 0V TO 10V
40
VIN = +5V VIN = +10V
20
0
-20
VIN = -10V VIN = -5V 200 300 400 500 600 700 800 900 1000 THROUGHPUT RATE (kSPS)
8194
8195
8196
CODE
Figure 10. Histogram of Codes for 200k Samples
06703-010
0
-40 100
Figure 12. Analog Input Current vs. Throughput Rate
Rev. 0 | Page 12 of 28
AD7366/AD7367
2.5050 2.5045 2.5040 2.5035
POWER (mV)
55 65 AVCC = 5V, DVCC = 5V VDD = 15V, VSS = -15V VDRIVE = 3V fS = 1MSPS INTERNAL REFERENCE 0V TO 10V RANGE
2.5030
VREF (V)
2.5025 2.5020 2.5015 2.5010 2.5005 2.5000 0 AVCC = 5V, DVCC = 5V VDD = 15V, VSS = -15V VDRIVE = 3V,
06703-013
45
5V RANGE
35 10V RANGE
25
10
20
30
40
50
60
70
80
90
200
300
400
500
600
700
800
900
1000
CURRENT LOAD (A)
SAMPLING FREQUENCY (kSPS)
Figure 13. VREF vs. Reference Output Current Drive
0.300
Figure 15. Power vs. Sampling Frequency in Normal Mode
0.250
VOUT OR VCC - VOUT (V)
SOURCE CURRENT
0.200 SINK CURRENT
0.150
0.100 AVCC = 5V, DVCC = 5V VDD = 15V, VSS = 15V VDRIVE = 3V, fS = 1MSPS INTERNAL REFERENCE 0 500 1000 1500 2000 2500
06703-014
0.50
0
CURRENT (A)
Figure 14. DOUT Source Current vs. (VCC - VOUT ) and DOUT Sink Current vs. VOUT
Rev. 0 | Page 13 of 28
06703-017
15 100
AD7366/AD7367 TERMINOLOGY
Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a single (1) LSB point below the first code transition and full scale, a point 1 LSB above the last code transition. Zero Code Error It is the deviation of the midscale transition (all 1s to all 0s) from the ideal VIN voltage, that is, AGND - 1/2 LSB for bipolar ranges and 2 x VREF - 1 LSB for the unipolar range. Positive Full-Scale Error It is the deviation of the last code transition (011...110) to (011...111) from the ideal (that is, +4 x VREF - 1 LSB or +2 x VREF - 1 LSB) after the zero code error has been adjusted out. Negative Full-Scale Error This is the deviation of the first code transition (10...000) to (10...001) from the ideal (that is, -4 x VREF + 1 LSB, -2 x VREF + 1 LSB, or AGND + 1 LSB) after the zero code error has been adjusted out. Zero Code Error Match This is the difference in zero code error across all 12 channels. Positive Full-Scale Error Match The difference in positive full-scale error across all channels. Negative Full-Scale Error Match The difference in negative full-scale error across all channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of a conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 LSB, after the end of conversion. Signal-to-Noise (+ Distortion) Ratio (SINAD) This ratio is the measured ratio of signal-to-noise (+ distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-noise (+ distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal-to-Noise (+ Distortion) = (6.02N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7366/AD7367, it is defined as:
THD(dB ) = 20 log V 2 2 + V3 2 + V 4 2 + V 5 2 + V 6 2 V1
where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic, or spurious noise, is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum. However, for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels when operating in any of the input ranges. It is measured by applying a full-scale, 150 kHz sine wave signal to all unselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure given is the typical across all four channels for the AD7366/AD7367 (see the Typical Performance Characteristics section for more information). Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum, and different frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa - fb), while the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). The AD7366/AD7367 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels.
Rev. 0 | Page 14 of 28
AD7366/AD7367
Power Supply Rejection Ration (PSRR) Variations in power supply affect the full-scale transition but not the converter's linearity. PSRR is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see Figure 11). Thermal Hysteresis Thermal hysteresis is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either T_HYS+ = +25C to TMAX to +25C or T_HYS- = +25C to TMIN to +25C It is expressed in ppm using the following equation:
VHYS ( ppm) =
VREF (25C ) - VREF (T _ HYS) x 10 6 VREF (25C )
where: VREF(25C) is VREF at 25C. VREF(T_HYS) is the maximum change of VREF at T_HYS+ or T_HYS-.
Rev. 0 | Page 15 of 28
AD7366/AD7367 THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7366/AD7367 are fast, dual, 2-channel, 12-/14-bit, bipolar input, simultaneous sampling, serial ADCs. The AD7366/AD7367 can accept bipolar input ranges of 10 V and 5 V. It can also accept a 0 V to 10 V unipolar input range. The AD7366/AD7367 requires VDD and VSS dual supplies for the high voltage analog input structure. These supplies must be equal to or greater than 11.5 V. See Table 7 for the minimum requirements on these supplies for each analog input range. The AD7366/AD7367 require a low voltage of 4.75 V to 5.25 V VCC supply to power the ADC core. Table 7. Reference and Supply Requirements for Each Analog Input Range
Selected Analog Input Range (V) 10 5 0 to 10 Reference Voltage (V) 2.5 3.0 2.5 3.0 2.5 3.0 Full-Scale Input Range (V) 10 12 5 6 0 to 10 0 to 12 AVCC (V) 5 5 5 5 5 5 Minimum VDD/VSS (V) 11.5 12 11.5 11.5 11.5 12
CONVERTER OPERATION
The AD7366/AD7367 have two successive approximation ADCs, each based around two capacitive DACs. Figure 16 and Figure 17 show simplified schematics of an ADC in acquisition and conversion phases. The ADC is comprised of control logic, a SAR, and a capacitive DAC. In Figure 16 (the acquisition phase), SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the signal on the input.
CAPACITIVE DAC A SW1 B CONTROL LOGIC SW2
06703-018
VIN
COMPARATOR AGND
Figure 16. ADC Acquisition Phase
The AD7366/AD7367 contain two on-chip, track-and-hold amplifiers, two successive approximation ADCs, and a serial interface with two separate data output pins. It is housed in a 24-lead TSSOP, offering the user considerable space-saving advantages over alternative solutions. The AD7366/AD7367 require a CNVST signal to start conversion. On the falling edge of CNVST both track-and-holds are placed into hold mode and the conversions are initiated. The BUSY signal goes high to indicate that the conversions are taking place. The clock source for each successive approximation ADC is provided by an internal oscillator. The BUSY signal goes low to indicate the end of conversion. On the falling edge of BUSY, the track-and-hold returns to track mode. Once the conversion is finished, the serial clock input accesses data from the part. The AD7366/AD7367 have an on-chip 2.5 V reference that can be disabled when an external reference is preferred. If the internal reference is to be used elsewhere in a system, then the output from DCAPA and DCAPB must first be buffered. On power-up, the REFSEL pin must be tied to either a high or low logic state to select either the internal or external reference option. If the internal reference is the preferred option, the user must tie the REFSEL pin logic high. Alternatively, if REFSEL is tied to GND then an external reference can be supplied to both ADCs through DCAPA and DCAPB pins. The analog inputs are configured as two single-ended inputs for each ADC. The various different input voltage ranges can be selected by programming the RANGE bits as shown in Table 8.
When the ADC starts a conversion (see Figure 17), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DAC is used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is balanced again, the conversion is complete. The control logic generates the ADC output code.
CAPACITIVE DAC A SW1 B CONTROL LOGIC SW2
06703-019
VIN
COMPARATOR AGND
Figure 17. ADC Conversion Phase
ANALOG INPUTS
Each ADC in the AD7366/AD7367 has two single-ended analog inputs. Figure 18 shows the equivalent circuit of the analog input structure of the AD7366/AD7367. The two diodes provide ESD protection. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward-biased and starts conducting current into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 170 . Capacitor C1 can primarily be attributed to pin capacitance while Capacitor C2 is the sampling capacitor of the ADC. The total lumped capacitance of C1 and C2 is approximately 9 pF for the 10 V input range and approximately 13 pF for all other input ranges.
Rev. 0 | Page 16 of 28
AD7366/AD7367
VDD D VIN0 C1 D VSS R1 C2
Table 10. LSB Sizes for Each Analog Input Range
Input Range 10 V 5 V 0 V to 10 V AD7366 Full-Scale LSB Size Range (mV) 20 V/4096 4.88 10 V/4096 2.44 10 V/4096 2.44 AD7367 Full-Scale LSB Size Range (mV) 20 V/16384 1.22 10 V/16384 0.61 10 V/16384 0.61
Figure 18. Equivalent Analog Input Structure
ADC CODE
The AD7366/AD7367 can handle true bipolar input voltages. The analog input can be set to one of three ranges: 10 V, 5 V, or 0 V to 10 V. The logic levels on Pin RANGE0 and Pin RANGE1 determine which input range is selected as outlined in Table 8. These range bits should not be changed during the acquisition time prior to a conversion, but can change at any other time. Table 8. Analog Input Range Selection
RANGE1 0 0 1 1 RANGE0 0 1 0 1 Range Selected 10 V 5 V 0 V to 10 V Do not program
06703-020
011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000 -FSR/2 + 1LSB +FSR/2 - 1LSB 0V ANALOG INPUT
06703-021
Figure 19. Transfer Characteristic
The AD7366/AD7367 require VDD and VSS dual supplies for the high voltage analog input structures. These supplies must be equal to or greater than 11.5 V. See Table 7 for the requirements on these supplies. The AD7366/AD7367 require a low voltage 4.75 V to 5.25 V AVCC supply to power the ADC core, a 4.75 V to 5.25 V DVCC supply for digital power, and a 2.7 V to 5.25 V VDRIVE supply for interface power. Channel selection is made via the ADDR pin as shown in Table 9. The logic level on the ADDR pin is latched on the rising edge of the BUSY signal for the next conversion, not the one in progress. When power is first supplied to the AD7366/AD7367 the default channel selection is VA1 and VB1. Table 9. Channel Selection
ADDR 0 1 Channels Selected VA1, VB1 VA2, VB2
Track-and-Hold
The track-and-hold on the analog input of the AD7366/AD7367 allows the ADC to accurately convert an input sine wave of fullscale amplitude to 12-/14-bit accuracy. The input bandwidth of the track-and-hold is greater than the Nyquist rate of the ADC. The AD7366/AD7367 can handle frequencies up to 35 MHz. The track-and-hold enters its tracking mode once the BUSY signal goes low after the CS falling edge. The time required to acquire an input signal depends on how quickly the sampling capacitor is charged. With zero source impedance, 140 ns is sufficient to acquire the signal to the 12-bit for the AD7366 and the 14-bit level for the AD7367. The acquisition time for the 10 V, 5 V, and 0 V to +10 V ranges to settle to within 1/2 LSB is typically 140 ns. The ADC goes back into hold mode on the falling edge of CNVST. The acquisition time required is calculated using the following formula: tACQ = 10 x ((RSOURCE + R) C) where: C is the sampling capacitance. R is the resistance seen by the track-and-hold amplifier looking at the input. RSOURCE should include any extra source impedance on the analog input.
TRANSFER FUNCTION
The output coding of the AD7366/AD7367 is twos complement. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent on the analog input range selected. The ideal transfer characteristic is shown in Figure 19.
Rev. 0 | Page 17 of 28
AD7366/AD7367
Unlike other bipolar ADCs, the AD7366/AD7367 do not have a resistive analog input structure. On the AD73667/AD7366, the bipolar analog signal is sampled directly onto the sampling capacitor. This gives the AD7366/AD7367 high analog input impedance. The analog input impedance can be calculated from the following formula: Z = 1/(fS x CS) where: fS is the sampling frequency. CS is the sampling capacitor value. CS depends on the analog input range chosen (see the Analog Inputs section). When operating at 1 MSPS, the analog input impedance is typically 260 k for the 10 V range. As the sampling frequency is reduced, the analog input impedance further increases. As the analog input impedance increases, the current required to drive the analog input therefore decreases (see Figure 7 for more information).
TYPICAL CONNECTION DIAGRAM
Figure 20 shows a typical connection diagram for the AD7366/ AD7367. In this configuration, the AGND pin is connected to the analog ground plane of the system, and the DGND pin is connected to the digital ground plane of the system. The analog inputs on the AD7366/AD7367 accept bipolar singleended signals. The AD7366/AD7367 can operate with either an internal or an external reference. In Figure 20, the AD7366/ AD7367 is configured to operate with the internal 2.5 V reference. A 680 nF decoupling capacitor is required when operating with the internal reference. The AVDD and DVDD pins are connected to a 5 V supply voltage. The VDD and VSS are the dual supplies for the high voltage analog input structures. The voltage on these pins must be equal to or greater than 11.5 V (see Table 8 for more information). The VDRIVE pin is connected to the supply voltage of the microprocessor. The voltage applied to the VDRIVE input controls the voltage of the serial interface. VDRIVE can be set to 3 V or 5 V.
+ 0.1F +11.5V TO +16.5V SUPPLY
+5V SUPPLY + 10F
+
10F
+
0.1F
+ 0.1F
VDD VA1 VA2
DVCC AVCC VDRIVE 0.1F CS SCLK CNVST DOUTA DOUTB BUSY ADDR REFSEL DGND AGND VDRIVE + 10F
+3V OR +5V SUPPLY +
MICROCONTROLLER/ MICROPROCESSOR
AD7366/ AD7367
ANALOG INPUTS 10V, 5V, AND 0V TO +10V
VB1 VB2 DCAP A 680nF + 680nF -16.5V TO -11.5V SUPPLY 10F + 0.1F + + DCAP B VSS
SERIAL INTERFACE
Figure 20. Typical Connection Diagram Using Internal Reference
Rev. 0 | Page 18 of 28
06703-022
AD7366/AD7367
DRIVER AMPLIFIER CHOICE
The AD7366/AD7367 have a total of four analog inputs, which operate in single-ended mode. Both ADC's analog inputs can be programmed to one of the three analog input ranges. In applications where the signal source is high impedance, it is recommended to buffer the signal before applying it to the ADC analog inputs. Figure 21 shows the configuration of the AD7366/AD7367 in single-ended mode. In applications where the THD and SNR are critical specifications, the analog input of the AD7366/AD7367 should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and can necessitate the use of an input buffer amplifier. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tolerated in the application. The THD increases as the source impedance increases and performance degrades. Figure 7 shows THD vs. the analog input frequency for various source impedances. Depending on the input range and analog input configuration selected, the AD7366/AD7367 can handle source impedances as illustrated in Figure 7. Due to the programmable nature of the analog inputs on the AD7366/AD7367, the choice of op amp used to drive the inputs is a function of the particular application and depends on the analog input voltage ranges selected. The driver amplifier must be able to settle for a full-scale step to a 14-bit level, 0.0061%, in less than the specified acquisition time of the AD7366/AD7367. An op amp such as the AD8021 meets this requirement when operating in single-ended mode. The AD8021 needs an external compensating NPO type of capacitor. The AD8022 can also be used in high frequency applications where a dual version is required. For lower frequency applications, recommended op amps are the AD797, AD845, and AD8610.
V+
VDRIVE
The AD7366/AD7367 also have a VDRIVE feature to control the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7366/AD7367 was operated with a VCC of 5 V, the VDRIVE pin could be powered from a 3 V supply, allowing a large dynamic range with low voltage digital processors. Thus, the AD7366/AD7367 could be used with the 10 V input range while still being able to interface to 3 V digital parts. To achieve the maximum throughput rate of 1.12 MSPS for the AD7366 or 1 MSPS for the AD7367, VDRIVE must be greater than or equal to 4.75 V, see Table 2 and Table 3. The maximum throughput rate with the VDRIVE voltage set to less than 4.75 V and greater than 2.7 V is 1 MSPS for the AD7366 and 900 kSPS for the AD7367.
REFERENCE
The AD7366/AD7367 can operate with either the internal 2.5 V on-chip reference or an externally applied reference. The logic state of the REFSEL pin determines whether the internal reference is used. The internal reference is selected for both ADC when the REFSEL pin is tied to logic high. If the REFSEL pin is tied to GND then an external reference can be supplied through the DCAPA and DCAPB pins. On power-up, the REFSEL pin must be tied to either a low or high logic state for the part to operate. Suitable reference sources for the AD7366/AD7367 include AD780, AD1582, ADR431, REF193, and ADR391. The internal reference circuitry consists of a 2.5 V band gap reference and a reference buffer. When operating the AD7366/ AD7367 in internal reference mode, the 2.5 V internal reference is available at the DCAPA and DCAPB pins, which should be decoupled to AGND using a 680 nF capacitor. It is recommended that the internal reference be buffered before applying it elsewhere in the system. The internal reference is capable of sourcing up to 150 A with an analog input range of 10 V and 70 A for both the 5 V and 0 V to 10 V ranges. If the internal reference operation is required for the ADC conversion, the REFSEL pin must be tied to logic high on powerup. The reference buffer requires 70 s to power up and charge the 680 nF decoupling capacitor during the power-up time. The AD7366/AD7367 is specified for a 2.5 V to 3 V reference range. When a 3 V reference is selected, the ranges are 12 V, 6 V, and 0 V to +12 V. For these ranges, the VDD and VSS supply must be equal to or greater than the +12 V and -12 V respectively.
+
10F +10V/+5V AGND -10V/-5V 1k 15pF + 0.1F VA1 VDD VCC
+5V
AD8021
+
AD7366/ AD7367*
+
VSS CCOMP = 10pF 0.1F 10F V-
06703-023
1k
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 21. Typical Connection Diagram with the AD8021 for Driving the Analog Input
+
Rev. 0 | Page 19 of 28
AD7366/AD7367 MODES OF OPERATION
The mode of operation of the AD7366/AD7367 is selected by the (logic) state of the CNVST signal at the end of a conversion. There are two possible modes of operation: normal mode and shutdown mode. These modes of operation are designed to provide flexible power management options, which can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. three-state, subsequently 12 SCLK cycles are required to read the conversion result from the AD7366 while 14 SCLK cycles are required to read from the AD7367. The DOUT lines return to three-state when CS is brought high only. If CS is left low for a further 12 SCLK cycles for the AD7366 or 14 SCLK cycles for the AD7367, the result from the other on chip ADC is also accessed on the same DOUT line, as shown in Figure 27 and Figure 28 (see the Serial Interface section). Once 24 SCLK cycles have elapsed for the AD7366 and 28 SCLK cycles for the AD7367, the DOUT line returns to threestate when CS is brought high and not on the 24th or 28th SCLK falling edge. If CS is brought high prior to this, the DOUT line returns to three-state at that point. Thus, CS must be brought high once the read is completed, as the bus does not automatically return to three-state upon completion of the dual result read. Once a data transfer is complete and DOUTA and DOUTB have returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CNVST low again.
NORMAL MODE
Normal mode is intended for applications needing fast throughput rates because the user does not have to worry about any power-up times (with the AD7366/AD7367 remaining fully powered at all times). Figure 22 shows the general mode of operation of the AD7366 in normal mode, while Figure 23 illustrates normal mode for the AD7367. The conversion is initiated on the falling edge of CNVST as described in the Circuit Information section. To ensure that the part remains fully powered up at all times, CNVST must be at logic state high prior to the BUSY signal going low. If CNVST is at logic state low when the BUSY signal goes low, the analog circuitry powers down and the part ceases converting. The BUSY signal remains high for the duration of the conversion. The CS pin must be brought low to bring the data bus out of
t1
CNVST
tQUIET
BUSY
t2 tCONVERT t3
CS
1
12
Figure 22. Normal Mode Operation for the AD7366
t1
CNVST
tQUIET
BUSY
t2 tCONVERT t3
CS
1
14
Figure 23. Normal Mode Operation for the AD7367
Rev. 0 | Page 20 of 28
06703-025
SCLK
SERIAL READ OPERATION
06703-024
SCLK
SERIAL READ OPERATION
AD7366/AD7367
SHUTDOWN MODE
Shutdown mode is intended for use in applications where slow throughput rates are required. Shutdown mode is suited to applications where a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and thus, shutdown. When the AD7366/AD7367 is in full power-down, all analog circuitry is powered down. The falling edge of CNVST initiates the conversion. The BUSY output subsequently goes high to indicate that the conversion is in progress. Once the conversion is completed, the BUSY output returns low. If the CNVST signal is at logic low when BUSY goes low then the part enters shutdown at the end of the conversion phase. While the part is in shutdown mode the digital output code from the last conversion on each ADC can still be read from the DOUT pins. To read the DOUT data, CS must be brought low as described in the Serial Interface section. The DOUT pins return to three-state once CS is brought back to logic high. To exit full power-down and to power up the AD7366/AD7367, a rising edge of CNVST is required. After the required power-up time has elapsed, CNVST may be brought low again to initiate another conversion, as shown in Figure 24 (see the Power-Up Times section for power-up times associated with the AD7366/ AD7367).
POWER-UP TIMES
The AD7366/AD7367 have one power down mode, which has already been described in detail in the Shutdown Mode section. This section deals with the power-up time required when coming out of this mode. It should be noted that the power-up times (as explained in this section) apply with the recommended capacitors in place on the DCAPA and DCAPB pins. To power up from shutdown, CNVST must be brought high and remain high for a minimum of 70 s, as shown in Figure 24. When power supplies are first applied to the AD7366/AD7367, the ADC can power up with CNVST in either the low or high logic state. Before attempting a valid conversion, CNVST must be brought high and remain high for the recommended powerup time of 70 s. Then CNVST can be brought low to initiate a conversion. With the AD7366/AD7367 no dummy conversion is required before valid data can be read from the DOUT pins. If it is intended to place the part in shutdown mode when the supplies are first applied, then the AD7366/AD7367 must be powered up and a conversion initiated. However, CNVST should remain in the logic low state and when the BUSY signal goes low, the part enters shutdown. Once supplies are applied to the AD7366/AD7367, sufficient time must be allowed for any external reference to power up and to charge the various reference buffer decoupling capacitors to their final values.
ENTERS SHUTDOWN CNVST BUSY
tPOWER-UP
t2 tCONVERT
CS SCLK 1
t3
SERIAL READ OPERATION 12
06703-026
Figure 24. Autoshutdown Mode for AD7366
Rev. 0 | Page 21 of 28
AD7366/AD7367 SERIAL INTERFACE
Figure 25 and Figure 26 show the detailed timing diagram for serial interfacing to the AD7366 and the AD7367. On the falling edge of CNVST the AD7366/AD7367 simultaneously converts the selected channels. These conversions are performed using the on-chip oscillator. After the falling edge of CNVST the BUSY signal goes high, indicating the conversion has started. It returns low once the conversion has been completed. The data can now be read from the DOUT pins. CS and SCLK signals are required to transfer data from the AD7366/AD7367. The AD7366/AD7367 have two output pins corresponding to each ADC. Data can be read from the AD7366/ AD7367 using both DOUTA and DOUTB. Alternatively, a single output pin of the user's choice can be used. The SCLK input signal provides the clock source for the serial interface. The CS goes low to access data from the AD7366/AD7367. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the conversion result. The data stream consists of 12 bits of data for the AD7366 and 14 bits of data for the AD7367, MSB first. The first bit of the conversion result is valid on the first SCLK falling edge after the CS falling edge. The subsequent 11-/13-bits of data for the AD7366/AD7367 respectively are clocked out on the falling edge of the SCLK signal. A minimum of 12 clock pulses must be provided to AD7366 to access each conversion result, while a minimum of 14 clock pulses must be provided to AD7367 to access the conversion result. Figure 25 shows how a 12 SCLK read is used to access the conversion results while Figure 26 illustrates the case for the AD7367 with a 14 SCLK read.
CS
On the rising edge of CS, the conversion is terminated and DOUTA and DOUTB go back into three-state. If CS is not brought high, but is instead held low for a further 12 SCLK cycles for the AD7366 or 14 SCLK cycles for the AD7367, on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This is illustrated in Figure 27 and Figure 28 where the case for DOUTA is shown. In this case, the DOUT line in use goes back into three-state on the rising edge of CS. If the falling edge of SCLK coincides with the falling edge of CS, then the falling edge of SCLK is not acknowledged by the AD7366/AD7367, and the next falling edge of the SCLK is the first registered after the falling edges of the CS. The CS pin can be brought low before the BUSY signal goes low indicating the end of a conversion. Once CS is at a logic low state the data bus is brought out of three-state. This feature can be utilized to ensure that the MSB is valid on the falling edge of BUSY by bring CS low a minimum of t4 nanoseconds before the BUSY signal goes low. The dotted CS line in Figure 22 and Figure 23 illustrates this. Alternatively, the CS pin can be tied to a low logic state continuously. Now the DOUT pins never enter three-state and the data bus is continuously active. Under these conditions, the MSB of the conversion result for the AD7366/AD7367 is available on the falling edge of the BUSY signal. The next most significant bit is available on the first SCLK falling edge after the BUSY signal has gone low. This mode of operation enables the user to read the MSB as soon as it is made available by the converter.
t8
SCLK 1 2 3 4 5 12
THREESTATE
DB10 DB11
DB9
DB8
DB2
DB1
DB0
THREE-STATE
Figure 25. Serial Interface Timing Diagram for the AD7366
CS
t8
SCLK 1 2 3 4 5 14
DB12 DB13
DB11
DB10
DB2
DB1
DB0
THREE-STATE
Figure 26. Serial Interface Timing Diagram for the AD7367
Rev. 0 | Page 22 of 28
06703-028
DOUTA DOUTB THREESTATE
t4
t5
t6
t7
t9
06703-027
DOUTA DOUTB
t4
t5
t6
t7
t9
AD7366/AD7367
CS
t8
SCLK 1 2 3 4 5 10 11 12 13 24
t4
DOUTA THREESTATE DB11A
DB10 A DB9 A
t5
t7
t6
THREESTATE
06703-030 06703-029
DB1 A
DB0 A
DB11B
DB10 B
DB1 B
DB0 B
Figure 27. Reading Data from Both ADCs on One DOUT Line with 24 SCLKs for the AD7366
CS
t8
SCLK 1 2 3 4 5 12 13 14 15 28
t3
DOUTA THREE- DB13 A STATE
DB12 A DB11A
t5
t7
t6
DB1 A DB0 A DB13 B DB12 B DB1 B DB0 B
THREESTATE
Figure 28. Reading Data from Both ADCs on One DOUT Line with 28 SCLKs for the AD7367
Rev. 0 | Page 23 of 28
AD7366/AD7367 MICROPROCESSOR INTERFACING
The serial interface on the AD7366/AD7367 allows the parts to be directly connected to a range of different microprocessors. This section explains how to interface the AD7366/AD7367 with some more common microcontrollers and DSP serial interface protocols.
AD7366/ AD7367*
ADSP-218x*
SCLK0 SCLK1 CS TFS0 RFS0 RFS1 DOUTA DOUTB BUSY CNVST VDRIVE DR0 DR1 IRQ FLO SCLK
AD7366/AD7367 TO ADSP-218x
The ADSP-218x family of DSPs interfaces directly to the AD7366/AD7367 without any glue logic required. The VDRIVE pin of the AD7366/AD7367 takes the same supply voltage as that of the ADSP-218x. This allows the ADC to operate at a higher supply voltage than its serial interface and therefore, the ADSP-218x, if necessary. This example shows both DOUTA and DOUTB of the AD7366/AD7367 connected to both serial ports of the ADSP-218x. The SPORT0 and SPORT1 control registers should be set up as shown in Table 11 and Table 12. Table 11. SPORT0 Control Register Setup
Setting TFSW = RFSW = 1 INVRFS = INVTFS = 1 DTYPE = 00 SLEN = 1111 ISCLK = 1 TFSR = RFSR = 1 IRFS = 0 ITFS = 1 Description Alternate framing Active low frame signal Right justify data 16-bit data-word (or can be set to 1101 for 14-bit data-word) Internal serial clock Frame every word
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 29. Interfacing the AD7366/AD7367 to the ADSP-218x
The AD7366/AD7367 BUSY line provides an interrupt to the ADSP-218x when the conversion is complete. The conversion results can then be read from the AD7366/AD7367 using a read operation. When an interrupt is received on IRQ from the BUSY signal, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and, hence, the reading of data.
AD7366/AD7367 TO ADSP-BF53x
The ADSP-BF53x family of DSPs interfaces directly to the AD7366/AD7367 without any glue logic required. The availability of secondary receive registers on the serial ports of the Blackfin(R) DSPs means only one serial port is necessary to read from both DOUTA and DOUTB pins simultaneously. Figure 30 shows both DOUTA and DOUTB of the AD7366/AD7367 connected to Serial Port 0 of the ADSP-BF53x. The SPORT0 Receive Configuration 1 register and SPORT0 Receive Configuration 2 register should be set up as outlined in Table 13 and Table 14.
AD7366/ AD7367*
DOUTA SCLK CS BUSY CNVST DOUTB VDRIVE SERIAL DEVICE B (SECONDARY)
06703-032
Table 12. SPORT1 Control Register Setup
Setting TFSW = RFSW = 1 INVRFS = INVTFS = 1 DTYPE = 00 SLEN = 1111 ISCLK = 0 TFSR = RFSR = 1 IRFS = 0 ITFS = 1 Description Alternate framing Active low frame signal Right justify data 16-bit data-word (or can be set to 1101 for 14-bit data-word) External serial clock Frame every word
SERIAL DEVICE A (PRIMARY)
ADSP-BF53x*
SPORT0 DR0PRI RCLK0 RFS0 RXINTS PFN DR0SEC
The connection diagram is shown in Figure 29. The ADSP-218x has the TFS0 and RFS0 of the SPORT0 and the RFS1 of SPORT1 tied together. TFS0 is set as an output, and both RFS0 and RFS1 are set as inputs. The DSP operates in alternate framing mode, and the SPORT control register is set up as described in Table 13 and Table 14. The frame synchronization signal generated on the TFS is tied to CS.
*ADDITIONAL PINS OMITTED FOR CLARITY.
VDD
Figure 30. Interfacing the AD7366/AD7367 to the ADSP-BF53x
Rev. 0 | Page 24 of 28
06703-031
VDD
AD7366/AD7367
Table 13. The SPORT0 Receive Configuration 1 Register (SPORT0_RCR1)
Setting RCKFE = 1 LRFS = 1 RFSR = 1 IRFS = 1 RLSBIT = 0 RDTYPE = 00 IRCLK = 1 RSPEN = 1 SLEN = 1111 TFSR = RFSR = 1 Description Sample data with falling edge of RSCLK Active low frame signal Frame every word Internal RFS used Receive MSB first Zero fill Internal receive clock Receive enabled 16-bit data-word (or can be set to 1101 for 14-bit data-word)
AD7366/ AD7367*
TMS320VC5506*
CLKX0 CLKR0 CLKX1 CLKR1 DOUTA DOUTB CS DR0 DR1 FSX0 FSR0 FSR1 BUSY CNVST VDRIVE
06703-033
SCLK
INTn XF
*ADDITIONAL PINS OMITTED FOR CLARITY.
VDD
Table 14. The SPORT0 Receive Configuration 2 Register (SPORT0_RCR2)
Setting RXSE = 1 SLEN = 1111 Description Secondary side enabled 16-bit data-word (or can be set to 1101 for 14-bit data-word)
Figure 31. Interfacing the AD7366/AD7367 to the TMS320VC5506
As with the previous interfaces, conversion can be initiated from the TMS320VC5506 or from an external source, and the processor is interrupted when the conversion sequence is completed.
AD7366/AD7367 TO DSP563xx
The connection diagram in Figure 32 shows how the AD7366/ AD7367 can be connected to the enhanced synchronous serial interface (ESSI) of the DSP563xx family of DSPs from Motorola. There are two on-board ESSIs, and each is operated in synchronous mode (Bit SYN = 1 in the CRB register) with internally generated word length frame sync for both TX and RX (Bit FSL1 = 0 and Bit FSL0 = 0 in the CRB register). Normal operation of the ESSI is selected by making MOD = 0 in the CRB register. Set the word length to 16 by setting Bit WL1 = 1 and Bit WL0 = 0 in the CRA register. The FSP bit in the CRB register should be set to 1 so that the frame sync is negative.
AD7366/AD7367 TO TMS320VC5506
The serial interface on the TMS320VC5506 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7366/AD7367. The CS input allows easy interfacing between the TMS320VC5506 and the AD7366/AD7367 without any glue logic required. The serial ports of the TMS320VC5506 are set up to operate in burst mode with internal CLKX0 (TX serial clock on Serial Port 0) and FSX0 (TX frame sync from Serial Port 0). The serial port control registers (SPC) must be setup as shown in Table 15. Table 15. Serial Port Control Register Set Up
SPC SPC0 SPC1 FO 0 0 FSM 1 1 MCM 1 0 TXM 1 0
The connection diagram is shown in Figure 31. The VDRIVE pin of the AD7366/AD7367 takes the same supply voltage as that of the TMS320VC5506. This allows the ADC to operate at a higher voltage than its serial interface and, therefore, the TMS320VC5506, if necessary.
Rev. 0 | Page 25 of 28
AD7366/AD7367
In the example shown in Figure 32, the serial clock is taken from the ESSI0 so the SCK0 pin must be set as an output (SCKD = 1) while the SCK1 pin is set as an input (SCKD = 0). The frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1, while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an input. The VDRIVE pin of the AD7366/AD7367 takes the same supply voltage as that of the DSP563xx. This allows the ADC to operate at a higher voltage than its serial interface and, therefore, the DSP563xx, if necessary.
AD7366/ AD7367*
SCLK
DSP563xx*
SCK0 SCK1
DOUTA DOUTB CS
SRD0 SRD1 SC02 SC12
BUSY CNVST VDRIVE
IRQN PBN
*ADDITIONAL PINS OMITTED FOR CLARITY.
VDD
Figure 32. Interfacing the AD7366/AD7367 to the DSP563xx
Rev. 0 | Page 26 of 28
06703-034
AD7366/AD7367 APPLICATION HINTS
LAYOUT AND GROUNDING
The printed circuit board that houses the AD7366/AD7367 should be designed so that the analog and digital sections are confined to their own separate areas of the board. This design facilitates the use of ground planes that can be easily separated. To provide optimum shielding for ground planes, a minimum etch technique is generally the best option. All AGND pins on the AD7366/AD7367 should be connected to the AGND plane. Digital and analog ground pins should be joined in only one place. If the AD7366/AD7367 are in a system where multiple devices require an AGND and DGND connection, the connection should still be made at only one point. A star point should be established as close as possible to the ground pins on the AD7366/AD7367. Good connections should be made to the power and ground planes. This can be done with a single via or multiple vias for each supply and ground pin. Avoid running digital lines under the AD7366/AD7367 devices because this couples noise onto the die. However, the analog ground plane should be allowed to run under the AD7366/ AD7367 to avoid noise coupling. The power supply lines to the AD7366/AD7367 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. To avoid radiating noise to other sections of the board, components, such as clocks, with fast switching signals should be shielded with digital ground and should never be run near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces should be run at right angles to each other. A microstrip technique is the best method, but its use may not be possible with a doublesided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the other side. Good decoupling is also important. All analog supplies should be decoupled with 10 F tantalum capacitors in parallel with 0.1 F capacitors to AGND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 F capacitors should have a low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic and surface mount types of capacitors. These low ESR, low ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
Rev. 0 | Page 27 of 28
AD7366/AD7367 OUTLINE DIMENSIONS
7.90 7.80 7.70
24
13
4.50 4.40 4.30
1 12
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7366BRUZ 1 AD7366BRUZ-RL71 AD7366BRUZ-500RL71 AD7367BRUZ1 AD7367BRUZ-500RL71 AD7367BRUZ-RL71 EVAL-AD7366CBZ EVAL-AD7367CBZ EVAL-CONTROL BRD2
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 24-Lead Thin Shrink Small Outline Package 24-Lead Thin Shrink Small Outline Package 24-Lead Thin Shrink Small Outline Package 24-Lead Thin Shrink Small Outline Package 24-Lead Thin Shrink Small Outline Package 24-Lead Thin Shrink Small Outline Package Evaluation Board Evaluation Board Control Board
Package Option RU-24 RU-24 RU-24 RU-24 RU-24 RU-24
Z = RoHS Compliant Part.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06703-0-5/07(0)
Rev. 0 | Page 28 of 28

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